oViCs introduces Frame Buffer Compression (FBC) IP core

oViCs Introduces Oz2, the Industry’s Most Efficient Frame Buffer Compression (FBC) IP core

SARATOGA, Calif. — oViCs, a leading provider of industry-standard advanced video IP cores for HEVC/H.265, today announced the release of Oz2, a Lossless Frame Buffer Compression IP core with fast, on-the-fly processing at memory speed that drastically reduces memory bandwidth and power consumption, typically by a factor of 3x.

Oz2 makes use of a proprietary patent pending algorithm that is context-based and adapts to local texture. The core can be configured to work on independent tiles for fast random access, or full frame for best compression results. The compression works statistically and is highly dependent on the content. When used with small tiles, the compression ranges from 1.6x to 6x (37% to 83% memory savings) and for full frame from 1.8x to 11x (44% to 91% memory savings).

“The importance of frame buffer compression has become critical in today’s complex SoC’s,” said Sorin Cismas, CEO and President of oViCs. “As the TV, tablets, and mobile display market evolves from HD to Ultra HD (4K) or even higher, bandwidth overhead and power consumption become a challenge. We have decided to productize and market our internally developed IP core used within our products. Oz2 is an optional core for the already available ViC-1 4Kp120 HEVC decoder and will be part of future oViCs products that will be announced later this year.”

oViCs IP cores are coded in Verilog RTL and are converted to C++, then compiled into 100% cycle accurate models. SoC manufacturers now have the ability to test complex bit streams and benchmark against internally developed or licensed IP. The simulators have proven to be excellent tools for customers to re-evaluate their existing solutions for efficiency, power and cost reductions. The offering of an actual 100% cycle accurate simulator for evaluation is among the many benefits and features that distinguish oViCs from the competition.