PathPartner Technology announces hybrid hardware-software HEVC decoder IP

Tuesday, September 23rd, 2014
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PathPartner Technology Announces Industry’s First Hybrid Hardware-Software HEVC Decoder Optimized for Programmable SoC Devices

  • Hybrid HEVC Decoder uses ARM CPU and FPGA fabric optimally enabling flexible, highly integrated video systems at lower overall system cost

BANGALORE — PathPartner Technology, a leading provider of embedded multimedia software services and solutions, announces the availability of Industry’s First Hybrid HEVC (H.265) Decoder partitioned optimally into ARM Cortex-A9 Software and FPGA Hardware on Xilinx Zynq-7000 All Programmable SoCs. This hybrid HEVC Decoder runs on a single chip delivering low power consumption and also the flexibility to integrate custom hardware blocks in the FPGA fabric on the same chip, thereby reducing overall system cost. Compared to pure hardware implementations that run on high-end FPGAs, this hybrid decoder uses the ARM CPU of Programmable SoC devices for highly sequential code like CABAC and hence uses less FPGA resources reducing power consumption and lowering cost.

Benefits of Hybrid HEVC Decoder on Programmable SoC for Video System Integrators

Since the hybrid HEVC decoder only uses a portion of the FPGA logic resources on the Zynq-7000 SoC, the remaining hardware resources can be used to integrate external display interfaces like DisplayPort, SD/HD/3G-SDI, LVDS for single or multi-panel displays for displaying the decoded video from the same chip. Compressed video can be brought to the HEVC decoder via standard interfaces like Gigabit Ethernet, USB 2.0, SD/MMC or PCI Express available as hardened blocks on the Zynq-7000 SoC. Besides, the HEVC decoder uses only one of the ARM Cortex-A9 CPUs in the Zynq-7000 SoC. The 2nd ARM CPU can be used for other software functions like handling network protocols, Graphics overlay, OS etc.

Key features of the Hybrid HEVC/H.265 Decoder:

  • Universal Main profile decoder – supports all features of Main profile as per latest HEVC (H.265) standard approved by ITU-T/ISO
  • Compliant to HM (JCT-VC reference code) version 13.0. Highly robust to error streams and supports high quality error concealment
  • Scalable from HD (1080p) to UltraHD (4K) Video Resolutions
  • Hardware part of decoder available with AXI4 Interfaces for easy integration into SoC
  • Software part of decoder available for Linux. Other OS/RTOS integration possible.
  • 1080p30 version of decoder runs on Xilinx Zynq Z7045 device at slowest speed grade and with less than 50% utilization of Hardware resources

Since HEVC (H.265) standard results in reduced bandwidth requirement as compared to H.264 for high resolution videos, it is popular in applications with wireless communication. Using SoC based FPGA chip enables usage of built-in interfaces like USB, SDIO in the Zynq SoC, along with custom hardware logic and wireless interfaces. This is particularly useful for defence and custom secure communication network based applications. “said Vinay Mangalore, VP of Engineering, PathPartner Technology.

“Xilinx welcomes PathPartner as a Member of the Xilinx Alliance Program and looks forward to providing the industry’s leading silicon platform for their IP development.” said Aaron Behman, Segment Lead, Broadcast and Professional A/V business at Xilinx.